IBM Spyre Dataflow Scheduler and KTIR
IBM's Apache-2.0 MLIR scheduler turns KTIR kernels into dataflow pipelines and SpyreCode for the Spyre accelerator.
Overview
A PyTorch blog post published around October 20, 2026 describes torch-spyre's backend compiler for IBM's Spyre accelerator. KTIR (Kernel Tile IR, RFC 0682) is an MLIR representation that records the work division and tensor placement Inductor has chosen. An open-source Dataflow Scheduler (github.com/torch-spyre/dataflow-scheduler, Apache-2.0) turns each KTIR kernel into a nested, double-buffered dataflow pipeline expressed as DataflowIR, and device-specific stages then produce SpyreCode. Spyre is described as 32 cores on a ring, each with 2 MB of scratchpad. Version 1 handles elementwise operations with broadcast and reduction dimensions; IBM says the first op came up about 4x faster than on the previous stack and later ops about 8x faster, with matrix multiplication and cost-model optimizations next.
This is a sourced directory entry. Features and capabilities are reported in the linked sources; this entry does not document independent Aymorphic testing.
Key features
- KTIR: tile-based MLIR IR with explicit memory spaces and distributed memory views
- Scheduler driven by an architecture-description file, so other dataflow devices can be targeted
- Splits kernels into programs, routes transfers through the memory hierarchy, nests and double-buffers pipelines
- Outputs DataflowIR, then symbolic SpyreBinary and a two-phase job plan (SpyreCode)
- Working paths from both Inductor and Triton frontends
Use cases
- Bringing up new operators on the Spyre accelerator behind torch.compile
- Reference design for compilers targeting scratchpad-based dataflow accelerators
Pricing
Free and open source (Apache-2.0 for the scheduler and its dialects).
Pricing reflects the source record and may change. Confirm current terms with the provider.
Dates and sources
- Released
- 20 Oct 2026
- Record updated
- 27 Oct 2026
- Record last checked
- 27 Oct 2026